library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity UART_FPGA_S3 is
  port (
    mclk : in std_logic;
    btn : in std_logic;
    rxd : in std_logic ;
    txd : out std_logic
  );
end UART_FPGA_S3;

architecture synthesis of UART_FPGA_S3 is

  component diviseurClk
    port (
      clk, reset : in  std_logic;
      nclk       : out std_logic);
    end component;
    
  component UARTunit
    port (
      clk, reset : in  std_logic;
      cs, rd, wr : in  std_logic;
      RxD        : in  std_logic;
      TxD        : out std_logic;
      IntR       : out std_logic;        
      IntT       : out std_logic;         
      addr       : in  std_logic_vector(1 downto 0);
      data_in    : in  std_logic_vector(7 downto 0);
      data_out   : out std_logic_vector(7 downto 0));
  end component;

  component echoUnit
    port (
      clk, reset : in  std_logic;
      cs, rd, wr : out  std_logic;
      IntR       : in std_logic;
      IntT       : in std_logic;
      addr       : out  std_logic_vector(1 downto 0);
      data_in    : in  std_logic_vector(7 downto 0);
      data_out   : out std_logic_vector(7 downto 0));
  end component;

  signal clkn : std_logic;
  signal cs, rd, wr : std_logic;
  signal intT, intR : std_logic;
  signal addresse : std_logic_vector(1 downto 0);
  signal d1, d2 : std_logic_vector(7 downto 0);

begin

  div : diviseurClk
    port map (mclk, not btn, clkn);
	  
  echo : echoUnit
    port map (clkn, not btn, cs, rd, wr, intR, intT, addresse, d1, d2);
	  
  uart : UARTunit
    port map( clkn, not btn, cs, rd, wr, rxd, txd, intR, intT, addresse, d2, d1);

end synthesis;
